1. Field of the Invention
The present invention relates to a semiconductor memory device and a parallel test therefor and, more specifically, to a semiconductor memory device and a structure of a parallel tester for performing test of semiconductor memory devices at a high speed.
2. Description of the Background Art
As memory capacity of a semiconductor memory device, specially of a dynamic type RAM (hereinafter referred to as a DRAM) has been increased, time necessary for testing the semiconductor memory device has been remarkably increased.
The reason why this problem occurs is that the more the storage capacity of the semiconductor memory device, the larger the number of word lines included therein, and therefore the longer becomes the time for writing and reading memory cell information while successively selecting the word lines.
The aforementioned problem is more serious in an acceleration test such as a burn in test. In the burn in test, a semiconductor memory device is operated under a high temperature and high voltage condition in order to reveal potential initial failure such as defect in gate insulating film of an MOS transistor, which is a component of the device, defect in an interlayer insulating film between interconnections, defect in interconnection and defect caused by particles introduced during the steps of manufacturing, and to eliminate defective products before shipment.
The above described burn in test is essential in maintaining quality of the products to be shipped. The increase in time for the test is directly related to increase of manufacturing cost of the semiconductor memory device.
The problem of longer test time is also experienced in a reliability test such as a life test.
FIG. 45 schematically shows a structure of a conventional apparatus for performing burn in test.
Referring to FIG. 45, on a test board TB, semiconductor memory devices DR11 to DRmn are arranged in a matrix of m rowsxc3x97n columns. The semiconductor memory devices DR11 to DRmn are connected to each other by a signal bus SG.
During testing, a control signal and a clock signal are output to test board TB from a test signal generating circuit TA. The control signal and the clock signal are transmitted to each semiconductor memory device by the signal bus SG.
In the burn in test, first, data at a high level is written to each memory cell of the semiconductor memory devices DR11 to DRmn. Thereafter, a row address strobe signal /RAS and an address signal are applied from test signal generating circuit TA to signal bus SG, and in semiconductor memory devices DR11 to DRmn, a word line is selected and sense amplifier circuit operates. The memory cell information amplified by the sense amplifier circuit is compared with the test data written in advance, and thus malfunction of each semiconductor memory device is detected.
The above described operation is continuously carried out for a prescribed time period under prescribed accelerating conditions.
FIG. 47 schematically shows a whole structure of a conventional dynamic semiconductor memory device. Referring to FIG. 47, the dynamic semiconductor memory device 1 includes a control circuit 18 receiving external control signals /WE, /OE, /RAS and /CAS applied through external control signal input terminals 2 to 5 for generating internal control signals; a memory cell array 7 in which memory cells are arranged in a matrix; an address buffer 9 receiving external address signals A0 to Ai applied through an address signal input terminal 8 for generating an internal row address signal and an internal column address signal under the control of the control circuit 18; an internal address generating circuit 10 for generating a refresh row address signal for designating a row to be refreshed during refreshing operation under the control of control circuit 18; a multiplexer 11 for selectively passing any of the address signals from address buffer 9 and internal address generating circuit 10 under the control of control circuit 18; and a row decoder 12 which is activated under the control of control circuit 18 for decoding the internal row address signal applied from multiplexer 11 to select a row of the memory cell array 7.
The signal /WE applied to external control signal input terminal 2 is a write enable signal designating data writing. The signal /OE applied to external control signal input terminal 3 is an output enable signal designating data output. The signal /RAS applied to the external control signal input terminal 4 is a row address strobe signal for starting internal operation in the semiconductor memory device and for determining active time period of the internal operation.
While the signal /RAS is active, circuits related to an operation of selecting a row in the memory cell array 7 are activated. The signal /CAS applied to external control signal input terminal 5 is a column address strobe signal, which activates a circuit for selecting a column in memory cell array 7.
Semiconductor memory device 1 further includes a column decoder 13 which is activated under the control of control circuit 18 for decoding an internal column address signal from address buffer 9 and generating a column selecting signal for selecting a column of the memory cell array 7; a sense amplifier sensing and amplifying data of a memory cell connected to the selected row of the memory array 7; an I0 gate responsive to a column selection signal from column decoder 13 for connecting the selected column of the memory cell array 7 to an internal data bus a1; an input buffer 15 for generating an internal write data from external write data DQ0 to DQj applied to data input terminal 17 at the time of data writing and transmitting thus generated data to internal data bus a1, under the control of control circuit 18; and an output buffer 16 for generating external read data DQ0 to DQj from internal read data read to internal data bus a1 at the time of data reading and outputting thus generated read data to data input/output terminal 17, under the control of control circuit 6.
Referring to FIG. 47, the sense amplifier and the IO gate are represented by one block 14. Input buffer 15 is activated when the signals /WE and /CAS are both at the active state of low level and generates the internal write data. Output buffer 16 is activated in response to the activation of the output enable signal /OE.
As described above, the operation of the DRAM is controlled by the aforementioned external signals /WE, /OE, /RAS and /CAS as well as address signals A0 to Ai.
Therefore, even in the burn in test, these signals are applied from test signal generating circuit TA to each of the semiconductor memory devices DR11 to DRmn.
In the above described burn in test, in order to suppress increase in test time even when the memory capacity of each semiconductor memory device is increased, the control signal /RAS transmitted from test signal generating circuit TA to signal bus SG shown in FIG. 45 may be changed at high speed, so as to shorten the time necessary for the word line to be selected.
However, a large number of semiconductor memory devices DR11 to DRmn are connected to signal bus SG, and there is a large parasitic capacitance Cp at signal bus SG, as shown in FIG. 45. Therefore, because of interconnection resistance and the large parasitic capacitance of the signal bus SG, there is a signal propagation delay, and hence increase in speed of changing said signal is limited.
FIG. 46 shows the change in the control signal /RAS and of the address signal on signal bus SG, as an example.
FIG. 46(A) shows an ideal signal waveform on signal bus SG, and FIG. 46(B) shows a signal waveform on signal bus SG in the conventional burn in test. As shown in FIG. 46(A), in the ideal state, the signal /RAS changes with a prescribed rise time and a prescribed fall time, not influenced by the signal propagation delay. The address signal requires a set up time Ts and a hold time Th with respect to the signal /RAS. The set up time Ts is necessary for the address signal to be in the established state before the fall of the signal /RAS. The hold time Th is necessary for maintaining the established state of the address signal from the fall of the signal /RAS.
If the signal bus SG has large parasitic capacitance Cp, the rise time and the fall time of the control signal /RAS become longer because of the signal propagation delay on signal bus SG, and the waveform is deformed as shown in FIG. 46(B). Therefore, it becomes impossible to change the control signal /RAS at high speed.
At this time, the speed of change of the address signal also becomes slower. In order to ensure the address set up time Ts, it is necessary to change the address signal at an earlier timing than the timing of change of the address signal in the ideal waveform (FIG. 46(A)). Since the address signal is changed while the control signal /RAS is at an inactive state of high level, the period in which the control signal /RAS is inactive becomes longer than in the ideal waveform.
As a result, the time period for one cycle (word line selection cycle) of the burn in test 1 becomes longer, the word lines cannot be successively selected at high speed, and hence the time necessary for the burn in test cannot be reduced.
In the burn in test, prescribed memory information is written in each memory cell in advance, and it is compared with an expected value which is the information successively read and written by successively selecting the word lines, so that data bit error is detected and defective products can be found. If it is difficult to change the control signal /RAS at a high speed as described above, the time necessary for the test is also increased since the time for the cycle of writing a signal, which is the aforementioned expected value in advance is increased.
Therefore, an object of the present invention is to provide a semiconductor memory device capable of executing test mode operation such as a burn in test at a high speed.
Another object of the present invention is to provide a parallel tester capable of reducing time when a plurality of semiconductor memory devices are tested, as the aforementioned signal with respect to each of the semiconductor memory devices can be changed at high speed.
A still further object of the present invention is to provide a semiconductor memory device capable of significantly reducing time for writing initial memory information, which will be an expected value in an operation test to each memory cell, and to provide a method of operation therefor.
Briefly speaking, in the present invention, clock generating circuitry which is activated in a test mode for generating an internal clock signal is provided in a semiconductor memory device, and the clock signal is utilized as a word line selecting operation activating signal.
More specifically, the semiconductor memory device in accordance with one aspect of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix; a clock generating circuit responsive to one external test mode designating signal for generating a clock signal of a prescribed period while the test mode designating signal is active; an internal address generating circuit responsive to the test mode designating signal and the clock signal for successively generating internal address signals in synchronization with the clock signal; an address signal switching circuit receiving the external address signal and the internal address signal, for outputting either of these in response to the test mode designating signal; and a row selecting circuit operating in synchronization with the clock signal for selecting, in response to an output from the address signal switching circuit, the corresponding row of the memory cell array.
According to another aspect of the present invention, a clock generating circuit which is activated in the test mode for generating an internal clock signal in synchronization with an externally applied clock signal is provided in the semiconductor memory device, and the internal clock signal is utilized as the word line selecting operation activating signal.
More specifically, the semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix; a first clock generating circuit responsive to an external test mode designating signal, for receiving an external clock signal and generating a first internal clock signal in synchronization with the external clock signal while the test mode designating signal is active; an internal address generating circuit responsive to the test mode designating signal and the first internal clock signal, for successively generating internal address signals in synchronization with the first internal clock signal; an address signal switching circuit receiving the external address signal and the internal address signal for outputting either of these in accordance with the test mode designating signal; and a row selecting circuit operating in synchronization with the clock signal and selecting a corresponding row of the memory cell array in accordance with the output from the address signal switching circuit.
According to a still further aspect of the present invention, an internal clock signal generating circuit which is activated in the test mode, receiving an external clock signal and generating an internal clock signal which is obtained by multiplying the external clock signal is provided in the semiconductor memory device, and the internal clock signal is utilized as the word line selecting operation activating signal.
More specifically, the semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix; a first clock generating circuit responsive to an external test mode designating signal for receiving an external clock signal and generating a first internal clock signal by multiplying said external clock signal while said test mode designating signal is active; an internal address generating circuit responsive to an operation mode designating signal and the first internal clock signal for successively generating internal address signals in synchronization with the first internal clock signal; an address signal switching circuit receiving the external address signal and the internal address signal for outputting either of these in response to the operation mode designating signal; and a row selecting circuit operating in synchronization with the clock signal for selecting a corresponding row of the memory cell array in accordance with the output from the address signal switching circuit.
According to a still further aspect of the present invention, when a plurality of semiconductor memory devices divided into a plurality of subgroups are to be subjected to operation test parallel to each other and in synchronization in accordance with an external clock signal, a circuit receiving the external clock signal for generating synchronized internal test clock signals for each subgroup is provided, and the semiconductor memory devices are tested in parallel at high speed.
More specifically, a parallel tester for performing operation test of a plurality of semiconductor memory devices in parallel and in synchronization in accordance with an externally input external clock signal includes an internal test clock generator provided for each subgroup of a plurality of semiconductor memory devices divided into a plurality of subgroups, receiving the external clock signal for generating a synchronized internal test clock signal; and a data bus line for transmitting the internal test clock signal to each of the semiconductor memory devices of the subgroup.
According to a still further aspect of the present invention, when data is to be written to the memory cell of the semiconductor memory device, the well potential of the memory cell transistor constituting the memory cell is controlled independent from the cell plate potential of a memory cell capacitor, so that memory information is written collectively.
More specifically, the semiconductor memory device according to this aspect includes: a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing the plurality of word lines and a plurality of memory cells connected to the word lines and the bit line pairs, each memory cell including a first electrode, a second electrode opposing to the first electrode with an insulating film interposed, and a memory cell transistor of a first conductivity type formed in a well of a second conductivity type, having its gate connected to the word line and connecting/disconnecting the second electrode to the bit line; the semiconductor memory device further includes a first interconnection commonly connected to the wells of the second conductivity type of the memory cells, a second interconnection commonly connected to the first electrodes of the memory cells and a potential controlling circuit capable of controlling the potentials of the first and second interconnections independent from each other.
Therefore, an advantage of the present invention is that acceleration test is possible without any influence of distortion in waveform of an external clock signal, since the clock generating circuit generates an internal clock signal of a prescribed period in accordance with one external test mode designating signal and the semiconductor memory device operates in accordance with the internal clock signal.
Another advantage is that acceleration test is possible without any influence of the distortion in waveform of the external clock signal, since, in accordance with an external test mode designating signal, a first internal clock signal in synchronization with the external clock signal is generated and semiconductor memory device operates accordingly.
A further advantage is that acceleration test is possible without any influence of distortion in the waveform of the external clock signal, since, in accordance with an external test mode designating signal, an internal clock signal is generated by multiplying an external clock signal and the semiconductor memory device operates accordingly.
A further advantage of the present invention is that even when a number of semiconductor memory devices are to be tested in parallel, distortion in clock signal applied to each of the semiconductor memory devices can be suppressed, since the plurality of semiconductor memory devices to be tested in parallel are divided into a plurality of subgroups, and an internal test clock generating circuit for generating, in response to an external clock signal, a synchronized internal test clock is provided for each subgroup of the semiconductor memory devices.
A still further advantage of the present invention is that memory information for testing can be written collectively to a plurality of memory cells, since well potentials and the plate potential of each memory cell is controlled independent from each other by a potential control circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.